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CY62256N
256K (32K x 8) Static RAM
Features
* Temperature Ranges -- Commercial: 0C to 70C -- Industrial: -40C to 85C -- Automotive-A: -40C to 85C -- Automotive-E: -40C to 125C * High speed: 55 ns * Voltage range: 4.5V-5.5V operation * Low active power -- 275 mW (max.) * Low standby power (LL version) -- 82.5 W (max.) * Easy memory expansion with CE and OE features * TTL-compatible inputs and outputs * Automatic power-down when deselected * CMOS for optimum speed/power * Available in pb-free and non Pb-free 28-lead (600-mil) PDIP, 28-lead (300-mil) narrow SOIC, 28-lead TSOP-I and 28-lead Reverse TSOP-I packages
Functional Description[1]
The CY62256N is a high-performance CMOS static RAM organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and tri-state drivers. This device has an automatic power-down feature, reducing the power consumption by 99.9% when deselected. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH.
Logic Block Diagram
INPUTBUFFER A10 A9 A8 A7 A6 A5 A4 A3 A2 CE WE OE A14 A13 A12 A11 A1 A0 ROW DECODER
I/O0 I/O1 SENSE AMPS I/O2 I/O3 I/O4 I/O5
32K x 8 Y ARRA
COLUMN DECODER
POWER DOWN
I/O6 I/O7
Note: 1. For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 001-06511 Rev. *A
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised August 3, 2006
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Product Portfolio
Power Dissipation VCC Range (V) Product CY62256NL CY62256NLL CY62256NLL CY62256NLL CY62256NLL Com'l / Ind'l Commercial Industrial Automotive-A Automotive-E Min. 4.5 Typ.[2] 5.0 Max. 5.5 Speed (ns) 70 70 55/70 55/70 55 Operating, ICC (mA) Typ.[2] 25 25 25 25 25 Max. 50 50 50 50 50 Standby, ISB2 (A) Typ.[2] 2 0.1 0.1 0.1 0.1 Max. 50 5 10 10 15
Pin Configurations
OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11
22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8
DIP Top View
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND
Narrow SOIC Top View
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3
TSOP I Top View (not to scale)
A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12
A11 A10 A9 A8 A7 A6 A5 VCC WE A4 A3 A2 A1 OE
7 6 5 4 3 2 1 28 27 26 25 24 23 22
8 9 10 11 12 13 14 15 16 17 18 19 20 21
TSOP I Reverse Pinout Top View (not to scale)
A12 A13 A14 I/O0 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 I/O7 CE A0
Pin Definitions
Pin Number 1-10, 21, 23-26 11-13, 15-19, 27 20 22 Type Input Input/Output Input/Control Input/Control Input/Control A0-A14. Address Inputs I/O0-I/O7. Data lines. Used as input or output lines depending on operation WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted CE. When LOW, selects the chip. When HIGH, deselects the chip OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins GND. Ground for the device Description
14 28
Ground
Power Supply VCC. Power supply for the device
Note: 2. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (TA = 25C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested.
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied..............................................-55C to +125C Supply Voltage to Ground Potential (Pin 28 to Pin 14) ........................................... -0.5V to +7.0V DC Voltage Applied to Outputs in High-Z State[3] ....................................-0.5V to VCC + 0.5V DC Input Voltage .................................-0.5V to VCC + 0.5V
[3]
Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Range Commercial Industrial Automotive-A Automotive-E Ambient Temperature (TA)[7] 0C to +70C -40C to +85C -40C to +85C -40C to +125C VCC 5V 10% 5V 10% 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range
-55 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current VCC Operating Supply Current GND < VI < VCC VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC L-Comm'l/ Ind'l LL-Comm'l LL - Ind'l LL - Auto-A LL - Auto-E ISB1 Automatic CE Power-down Current-- TTL Inputs Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX L LL-Comm'l LL - Ind'l LL - Auto-A LL - Auto-E ISB2 Automatic CE Power-down Current-- CMOS Inputs Max. VCC, CE > VCC - 0.3V VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 L LL-Comm'l LL - Ind'l LL - Auto-A LL - Auto-E 0.1 0.1 0.1 10 10 15 0.3 0.3 0.3 0.5 0.5 0.5 2 0.1 0.1 0.1 50 5 10 10 25 25 25 50 50 50 0.4 0.3 0.3 0.3 0.6 0.5 0.5 0.5 Output Leakage Current GND < VO < VCC, Output Disabled Test Conditions VCC = Min., IOH = -1.0 mA VCC = Min., IOL = 2.1 mA 2.2 -0.5 -0.5 -0.5 Min. Typ. 2.4 0.4 VCC +0.5V 0.8 +0.5 +0.5 2.2 -0.5 -0.5 -0.5 25 25 25 25
[2]
-70 Max. Min. Typ.[2] 2.4 0.4 VCC +0.5V 0.8 +0.5 +0.5 50 50 50 50 Max. Unit V V V V A A mA mA mA mA mA mA mA mA mA mA A A A A A
Capacitance[8]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 6 8 Unit pF pF
Notes: 3. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 4. TA is the "Instant-On" case temperature. 5. Tested initially and after any design or process changes that may affect these parameters.
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Thermal Resistance[5]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board DIP 75.61 43.12 SOIC 76.56 36.07 TSOP 93.89 24.64 RTSOP 93.89 24.64 Unit C/W C/W
AC Test Loads and Waveforms
R1 1800 5V OUTPUT 100 pF INCLUDING JIG AND SCOPE R2 990 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 990 3.0V 10% GND < 5 ns R1 1800 ALL INPUT PULSES 90% 90% 10% < 5 ns
(a)
(b)
Equivalent to: THE VENIN EQUIVALENT 639 OUTPUT 1.77V
Data Retention Characteristics
Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current L LL-Comm'l LL - Ind'l/Auto-A LL - Auto-E tCDR[8] tR[8] Chip Deselect to Data Retention Time Operation Recovery Time 0 tRC VCC = 2.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V Conditions[6] Min. 2.0 2 0.1 0.1 0.1 50 5 10 10 Typ.[2] Max. Unit V A A A A ns ns
Data Retention Waveform
DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR
Note: 6. No input may exceed VCC + 0.5V.
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Switching Characteristics Over the Operating Range[7]
CY62256N-55 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z
[8]
CY62256N-70 Min. 70 Max. Unit ns 70 5 70 35 5 25 5 25 0 70 70 60 60 0 0 50 30 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 25 5 ns ns
Description
Min. 55
Max.
55 5 55 25 5 20 5 20 0 55 55 45 45 0 0 40 25 0 20 5
OE HIGH to High-Z[8, 9] CE LOW to Low-Z[8] CE HIGH to High-Z[8, 9] CE LOW to Power-up CE HIGH to Power-down
[10, 11]
Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to WE HIGH to High-Z[8, 9] Low-Z[8]
Switching Waveforms
Read Cycle No. 1[12, 13]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Notes: 7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write. 11. The minimum Write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 12. Device is continuously selected. OE, CE = VIL. 13. WE is HIGH for Read cycle.
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Switching Waveforms (continued)
Read Cycle No. 2[13, 14]
CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tPD ICC 50% ISB tHZOE tHZCE DATA VALID tRC
HIGH IMPEDANCE
DATA OUT
Write Cycle No. 1 (WE Controlled)[10, 15, 16]
tWC ADDRESS
CE tAW WE tSA tPWE tHA
OE tSD DATA I/O NOTE 17 tHZOE DATAIN VALID tHD
Write Cycle No. 2 (CE Controlled)[10, 15, 16]
tWC ADDRESS CE tSA tAW WE tSD DATA I/O DATA VALID IN tHD tHA tSCE
Notes: 14. Address valid prior to or coincident with CE transition LOW. 15. Data I/O is high impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 17. During this period, the I/Os are in output state and input signals should not be applied.
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Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[11, 16]
tWC ADDRESS
CE tAW WE tSA tHA
tSD DATA I/O NOTE 17 tHZWE DATA VALID IN
tHD
tLZWE
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CY62256N
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 NORMALIZED ICC, ISB 1.2 NORMALIZED ICC 1.0 0.8 0.6 0.4 0.2 0.0 4.0 ISB 4.5 5.0 5.5 6.0 VIN = 5.0V TA = 25C ICC 1.4 1.2 1.0 ISB2 A 0.8 0.6 0.4 0.2 0.0 SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED tAA NORMALIZED tAA 1.3 1.2 1.1 TA = 25C 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 1.6 1.4 1.2 1.0 VCC = 5.0V 0.8 0.6 SUPPLY VOLTAGE (V) VCC = 5.0V VIN = 5.0V NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE ICC 3.0 2.5 2.0 1.5 1.0 0.5 0.0 25 125 -0.5 VCC = 5.0V VIN = 5.0V 25 105 ISB STANDBY CURRENT vs. AMBIENT TEMPERATURE
-55
-55
AMBIENT TEMPERATURE (C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (C) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC = 5.0V TA = 25C
-55
25
125
OUTPUT SINK CURRENT (mA)
AMBIENT TEMPERATURE (C) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC = 5.0V TA = 25C
OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT (mA)
OUTPUT VOLTAGE (V)
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Typical DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 NORMALIZED IPO DELTA tAA (ns) 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 30.0 NORMALIZED ICC 25.0 20.0 15.0 10.0 5.0 0.0 0 200 400 VCC = 4.5V TA = 25C TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25 VCC = 5.0V TA = 25C VIN = 5.0V NORMALIZED ICC vs. CYCLE TIME
1.00
0.75
600
800 1000
0.50 10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Truth Table
CE H L L L WE X H L H OE X L X H Inputs/Outputs High-Z Data Out Data In High-Z Read Write Output Disabled Mode Deselect/Power-down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
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Ordering Information
Speed (ns) 55 Ordering Code CY62256NLL-55SNI CY62256NLL-55SNXI CY62256NLL-55ZI CY62256NLL-55ZXI CY62256NLL-55ZXA CY62256NLL-55SNXE CY62256NLL-55ZXE CY62256NLL-55ZRXE 70 CY62256NL-70PC CY62256NL-70PXC CY62256NLL-70PC CY62256NLL-70PXC CY62256NL-70SNC CY62256NL-70SNXC CY62256NLL-70SNC CY62256NLL-70SNXC CY62256NLL-70ZC CY62256NLL-70ZXC CY62256NL-70SNI CY62256NL-70SNXI CY62256NLL-70SNI CY62256NLL-70SNXI CY62256NLL-70ZI CY62256NLL-70ZXI CY62256NLL-70ZRI CY62256NLL-70ZRXI CY62256NLL-70SNXA 51-85092 51-85074 51-85071 51-85092 51-85071 51-85092 51-85071 51-85092 51-85071 51-85074 51-85017 51-85071 Package Diagram 51-85092 Package Type 28-lead (300-Mil) Narrow SOIC 28-lead (300-Mil) Narrow SOIC (Pb-Free) 28-lead TSOP I 28-lead TSOP I (Pb-Free) 28-lead TSOP I (Pb-Free) 28-lead (300-Mil) Narrow SOIC (Pb-Free) 28-lead TSOP I (Pb-Free) 28-lead Reverse TSOP I (Pb-Free) 28-lead (600-Mil) Molded DIP 28-lead (600-Mil) Molded DIP (Pb-Free) 28-lead (600-Mil) Molded DIP 28-lead (600-Mil) Molded DIP (Pb-Free) 28-lead (300-Mil) Narrow SOIC 28-lead (300-Mil) Narrow SOIC (Pb-Free) 28-lead (300-Mil) Narrow SOIC 28-lead (300-Mil) Narrow SOIC (Pb-Free) 28-lead TSOP I 28-lead TSOP I (Pb-Free) 28-lead (300-Mil) Narrow SOIC 28-lead (300-Mil) Narrow SOIC (Pb-Free) 28-lead (300-Mil) Narrow SOIC 28-lead (300-Mil) Narrow SOIC (Pb-Free) 28-lead TSOP I 28-lead TSOP I (Pb-Free) 28-lead Reverse TSOP I 28-lead Reverse TSOP I (Pb-Free) 28-lead (300-Mil) Narrow SOIC (Pb-Free) Automotive-A Industrial Commercial Automotive-A Automotive-E Operating Range Industrial
Please contact your local Cypress sales representative for availability of these parts
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Package Diagrams
28-lead (600-Mil) Molded DIP (51-85017)
14 1
DIMENSIONS IN INCHES REFERENCE JEDEC Ms-020
MIN. MAX.
0.530 0.550
15
28
0.070 0.090 SEATING PLANE 0.600 0.625
1.380 1.480 0.155 0.200 0.115 0.160 0.090 0.110 0.055 0.065 0.014 0.022 0.140 0.195
0.009 0.012 0.015 0.060 0.610 0.700
51-85017-*B
3 MIN.
28-lead (300-mil) SNC (Narrow Body) (51-85092)
51-85092-*B
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Package Diagrams (continued)
28-lead TSOP I (8 x 13.4 mm) (51-85071)
51-85071-*G
28-Lead RTSOP I (8 x 13.4 mm) (51-85074)
51-85074-*F
All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 001-06511 Rev. *A Page 12 of 13
(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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Document History Page
Document Title: CY62256N 256K (32K x 8) Static RAM Document Number: 001- 06511 REV. ** *A ECN NO. 426504 488954 Issue Date See ECN See ECN Orig. of Change NXR NXR New Data Sheet Added Automotive product Updated ordering Information table Description of Change
Document #: 001-06511 Rev. *A
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